1.1.1 Structure and Function of the Processor
1.1.1(a) Processor Components
The processor (CPU - Central Processing Unit) is the brain of a computer system, responsible for executing instructions that allow programs to function.
ALU (Arithmetic and Logic Unit)
Definition
The ALU performs all arithmetic and logical operations within the CPU.
Arithmetic operations: Addition, subtraction, multiplication, division
Logical operations: AND, OR, NOT, XOR (Boolean logic)
Arithmetic operations: Addition, subtraction, multiplication, division
Logical operations: AND, OR, NOT, XOR (Boolean logic)
CU (Control Unit)
Definition
The Control Unit manages and coordinates all operations of the CPU.
Key Point
CU Responsibilities:
• Directing the flow of data between the CPU and other components
• Coordinating the sequence of data processing steps
• Sending control signals to manage instruction execution
• Directing the flow of data between the CPU and other components
• Coordinating the sequence of data processing steps
• Sending control signals to manage instruction execution
Registers
Definition
High-speed storage locations within the CPU that temporarily hold data being processed. Much faster than RAM.
| Register | Full Name | Purpose |
|---|---|---|
| PC | Program Counter | Stores the address of the next instruction to be executed |
| ACC | Accumulator | Holds results of arithmetic and logic operations |
| MAR | Memory Address Register | Contains the address of the memory location to be read/written |
| MDR | Memory Data Register | Temporarily stores data being transferred to/from memory |
| CIR | Current Instruction Register | Stores the instruction currently being executed (split into opcode and operand) |
Exam Tip
You must know what each register does. A common exam question asks you to describe how specific registers are used during the FDE cycle.
Buses
Definition
Communication channels that transfer data between different parts of the computer.
| Bus | Direction | Purpose |
|---|---|---|
| Data Bus | Bi-directional | Carries data and instructions between components |
| Address Bus | Unidirectional (CPU → Memory) | Carries memory addresses to identify where data should be read/written |
| Control Bus | Bi-directional | Carries control signals (read, write, clock) to coordinate actions |
Key Point
Bus Width: The width of the address bus determines how many memory locations can be addressed.
1.1.1(b) The Fetch-Decode-Execute Cycle
Definition
The fundamental process by which the CPU retrieves, interprets, and carries out instructions from memory, one after another.
FETCH Phase
- 1.The address in the PC (address of the next instruction) is copied to the MAR
- 2.The instruction at that address is fetched from RAM into the MDR
- 3.The PC is incremented (PC + 1) to point to the next instruction
- 4.The instruction is copied from the MDR to the CIR (ready for decoding_)
DECODE Phase
- 5.The instruction in the CIR is split into opcode (operation) and operand (data/address)
- 6.The Control Unit decodes the opcode to determine what operation to perform
EXECUTE Phase
- 7.The instruction is executed - this may involve:
Worked Example
Worked Example: Executing LDA 15
Let's trace through the FDE cycle for the instruction "LDA 15" (Load the value from memory address 15 into the Accumulator).
Initial State:
• PC = 100 (next instruction is at address 100)
• ACC = 0
FETCH Phase:
1. PC (100) is copied to MAR
2. Address 100 sent along address bus
3. Read signal sent on control bus
4. Instruction "LDA 15" fetched from memory to MDR
5. PC incremented to 101
6. "LDA 15" copied from MDR to CIR
DECODE Phase:
7. CIR splits into: opcode = "LDA", operand = "15"
8. Control Unit decodes: "LDA" = Load value from memory address into ACC
EXECUTE Phase:
9. Operand (15) copied to MAR
10. Address 15 sent along address bus
11. Read signal sent on control bus
12. Value at address 15 fetched to MDR (let's say value is 42)
13. Value (42) copied from MDR to ACC
Final State:
• PC = 101 (ready for next instruction)
• ACC = 42 (loaded from memory)
• MAR = 15
• MDR = 42
Key Point: Notice how the FDE cycle uses registers and buses in a specific sequence. The MAR and MDR are used twice - first to fetch the instruction, then to fetch the data.
Let's trace through the FDE cycle for the instruction "LDA 15" (Load the value from memory address 15 into the Accumulator).
Initial State:
• PC = 100 (next instruction is at address 100)
• ACC = 0
FETCH Phase:
1. PC (100) is copied to MAR
2. Address 100 sent along address bus
3. Read signal sent on control bus
4. Instruction "LDA 15" fetched from memory to MDR
5. PC incremented to 101
6. "LDA 15" copied from MDR to CIR
DECODE Phase:
7. CIR splits into: opcode = "LDA", operand = "15"
8. Control Unit decodes: "LDA" = Load value from memory address into ACC
EXECUTE Phase:
9. Operand (15) copied to MAR
10. Address 15 sent along address bus
11. Read signal sent on control bus
12. Value at address 15 fetched to MDR (let's say value is 42)
13. Value (42) copied from MDR to ACC
Final State:
• PC = 101 (ready for next instruction)
• ACC = 42 (loaded from memory)
• MAR = 15
• MDR = 42
Key Point: Notice how the FDE cycle uses registers and buses in a specific sequence. The MAR and MDR are used twice - first to fetch the instruction, then to fetch the data.
Exam Tip
Common Mistake: Students often forget that the PC is incremented during the FETCH phase, not after EXECUTE. The PC always points to the NEXT instruction.
1.1.1(c) Factors Affecting CPU Performance
Clock Speed
Definition
The number of cycles the CPU can perform per second, measured in Hertz (Hz). Modern CPUs are measured in GHz (billions of cycles per second).
Example
A 3.5 GHz processor can perform 3.5 billion cycles per second.
| Advantage | Disadvantage |
|---|---|
| More instructions executed per second | Generates more heat |
| Faster program execution | Higher power consumption |
| Diminishing returns at very high speeds |
Number of Cores
Definition
A CPU containing multiple independent processing units (cores), each capable of executing instructions independently.
| Advantage | Disadvantage |
|---|---|
| Parallel processing - multiple tasks simultaneously | Software must be written to utilise multiple cores |
| Better multitasking performance | Not all tasks can be parallelised |
| More efficient than increasing clock speed | Increased complexity and cost |
Key Point
Doubling the cores does NOT double performance. Performance gain depends on how well software can split tasks across cores.
Cache Memory
Definition
Small, extremely fast volatile memory located on or near the CPU that stores frequently accessed data and instructions.
| Level | Size | Speed | Location |
|---|---|---|---|
| L1 | Smallest (32-64KB) | Fastest | On CPU core |
| L2 | Medium (256KB-1MB) | Fast | On CPU (per core or shared) |
| L3 | Largest (2-32MB) | Slower than L1/L2 | Shared between all cores |
Key Point
Cache reduces the time spent waiting for data from RAM. A cache hit (data found in cache) is much faster than a cache miss (data must be fetched from RAM).
1.1.1(d) Pipelining
Definition
A technique that improves CPU efficiency by overlapping the execution of multiple instructions. While one instruction is being executed, the next is being decoded, and another is being fetched.
| Cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
|---|---|---|---|---|---|---|---|---|---|
| Inst 1 | F | D | E | ||||||
| Inst 2 | F | D | E | ||||||
| Inst 3 | F | D | E |
| Cycle | 1 | 2 | 3 | 4 | 5 |
|---|---|---|---|---|---|
| Inst 1 | F | D | E | ||
| Inst 2 | F | D | E | ||
| Inst 3 | F | D | E |
3 instructions complete in 5 cycles instead of 9!
| Advantage | Disadvantage |
|---|---|
| Increases instruction throughput | Pipeline stalls if one stage takes longer |
| Better utilisation of CPU components | Branch instructions cause pipeline flushes |
| No increase in clock speed needed | Adds complexity to CPU design |
1.1.1(e) Processor Architectures
Von Neumann Architecture
Definition
A computer architecture where both data and instructions are stored in the same memory and travel along the same bus.
Key Point
Von Neumann Bottleneck: Since data and instructions share the same bus, they cannot be fetched simultaneously. This creates a bottleneck that limits performance.
Harvard Architecture
Definition
A computer architecture with separate memory and buses for data and instructions, allowing both to be fetched simultaneously.
Von Neumann vs Harvard Comparison
| Feature | Von Neumann | Harvard |
|---|---|---|
| Memory | Single memory for data & instructions | Separate memory for data & instructions |
| Buses | Shared data/instruction bus | Separate data and instruction buses |
| Fetch | Cannot fetch data & instruction simultaneously | Can fetch data & instruction simultaneously |
| Speed | Slower (bottleneck) | Faster (parallel fetching) |
| Complexity | Simpler, cheaper | More complex, expensive |
| Use | General-purpose computers | DSPs, microcontrollers, embedded systems |
Key Point
Modern CPUs use a hybrid approach: Harvard architecture for cache (separate L1 instruction and data caches) but Von Neumann for main memory.
Exam Tip
A common exam question asks you to compare Von Neumann and Harvard architectures. Always mention: separate/shared memory, the bottleneck, and simultaneous fetching.