1.1.1 Structure and Function of the Processor Exam Questions
Paper 1 · Computer Systems · 16 past paper questions · 37 marks
Exam questions for 1.1.1 Structure and function of the processor
16 OCR past paper questions (37 marks) with mark schemes
Answer each question, reveal the mark scheme, then award yourself marks. Scores and answers are saved in this browser so you can see which topics need more work.
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- Question 1H446/01 · June 20244 marks
The stored program concept uses the Fetch-Decode-Execute cycle to get the next instruction from memory and then execute it. Describe what happens during the fetch stage of the Fetch-Decode-Execute cycle. You should state the different registers and buses that are used in your answer.
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1 mark per bullet to max 4: • The contents of the Program Counter/PC are copied/sent to the Memory Address Register/MAR • The address is sent/transferred along the address bus • The control unit sends/transfers a (read) signal along the control bus • Contents stored in the memory address are sent/transferred along the data bus • Contents (from memory) are stored in the Memory Data Register/MDR • ...and sent/copied to the Current Instruction Register/CIR • The Program Counter/PC is incremented Accept IR/Instruction Register for CIR/Current instruction Register Accept MBR/Memory Buffer Register for MDR/Memory Data RegisterMark yourself: how many marks did you get?/ 4 - Question 2H446/01 · June 20241 mark
One of the instructions that may be fetched and executed as part of this cycle is a branch instruction. State the name of the register that would be altered in the execute phase during a branch instruction.
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Program Counter // PC (1 mark)Mark yourself: how many marks did you get?/ 1 - Question 3H446/01 · June 20243 marks
Three ways of improving the performance of a CPU are increasing the clock speed, adding more cores and using pipelining. Explain how pipelining improves the performance of a CPU.
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1 mark per bullet: • Allows the next instruction to be fetched whilst the previous one is being decoded/executed // allows the overlapping of different parts of the FDE • It increases throughput // increases the number of instructions processed in a set period of time • It prevents the CPU having to wait // prevents idle components Allow a diagram demonstrating pipelining for MP1. Allow 'it will take less time to do the same amount of instructions' for MP2.Mark yourself: how many marks did you get?/ 3 - Question 4H446/01 · June 20222 marks
A charity is concerned that the performance of a computer is not sufficient and wishes to replace the processor. Give two features of a replacement processor that would increase the typical performance of the computer.
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Higher/faster clock speed More cores//dual/quad/etc core More cache memory. (2 marks - 1 for each valid feature) Answers must refer to an improvement (more/higher/faster) not just "change the clock speed" Allow discussions of level 1/level 2 cache sizes for one mark. Accept valid features: Pipelining, Simultaneous Multithreading Do not accept RISC/CISC.Mark yourself: how many marks did you get?/ 2 - Question 5H446/01 · June 20222 marks
The processor contains registers including the accumulator and the program counter. The contents of these registers are modified during the Fetch-Decode-Execute cycle. Describe how the accumulator is used during the Fetch-Decode-Execute cycle.
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Holds all input/output Holds results of calculations (from the ALU) Checked for conditional branching (e.g. BRZ) Stores data which has come from the MDR/RAM (2 marks - max 2 from list)Mark yourself: how many marks did you get?/ 2 - Question 6H446/01 · June 20222 marks
Describe how the program counter is used during the Fetch-Decode-Execute cycle.
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Holds the address/location of the next instruction (to be executed/fetched) Contents copied to the MAR at start of FDE Incremented (by one) on every cycle Can be changed by branch/jump instructions (2 marks - max 2 from list)Mark yourself: how many marks did you get?/ 2 - Question 7H446/01 · June 20223 marks
State the name of three other registers that are used during the Fetch-Decode-Execute cycle.
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Memory Address Register // MAR Memory Data Register // MDR Current Instruction Register // CIR Index Register // IR (3 marks - 1 for each, max 3) Allow Memory Buffer Register for MDRMark yourself: how many marks did you get?/ 3 - Question 8H446/01 · June 20222 marks
A charity uses a desktop computer to record financial donations that it receives. The computer contains a single core, 2.4GHz processor with 2MB cache. A processor uses the Von Neumann architecture. Describe what is meant by the term 'Von Neumann architecture'.
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Both data and instructions share the same memory Instructions and Data stored in same format A single set of buses / same bus for instructions & data (to connect CPU to Memory and I/O) Has a (single) control unit Has an ALU Has ways to input and output Has access to storage Works sequentially through instructions // follows Fetch-execute cycle (Special) registers within CPU Based on stored program concept (2 marks - max 2 from list)Mark yourself: how many marks did you get?/ 2 - Question 9H446/01 · June 20221 mark
Give one way that the Harvard architecture differs from the Von Neumann architecture.
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Separate memory for data and instructions / Multiple memory units Different (sets of) buses one for instructions & one for data / instructions and data can be accessed concurrently. (1 mark)Mark yourself: how many marks did you get?/ 1 - Question 10H446/01 · June 20213 marks
The CPU uses pipelining to improve efficiency. Explain what is meant by the term 'pipelining'.
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Concurrent processing of multiple instructions One instruction can be fetched while previous is being decoded And the one before is being executed In case of a branch pipeline is flushed Increases speed of execution (3 marks - max 3 from list)Mark yourself: how many marks did you get?/ 3 - Question 11H446/01 · June 20212 marks
OCR Insurance uses a computer system to calculate the price that customers pay for car insurance. The computer system contains a CPU, GPU, RAM and ROM. State two factors that affect the performance of a CPU.
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Clock speed Number of cores Cache Use of pipelining/size of pipeline Use of out of order execution Use of SIMD instructions Integrated graphics processing on CPU (2 marks - 1 for each, max 2)Mark yourself: how many marks did you get?/ 2 - Question 12H446/01 · June 20182 marks
A digital coffee making machine has a CPU that uses the Little Man Computer Instruction Set. Little Man Computer operates on a computer system based on the Von Neumann Architecture. State two features of the Von Neumann architecture.
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(Single) Control Unit (Single) Arithmetic Logic Unit (Special) registers within CPU Instructions and Data stored in same area of memory Instructions and Data stored in same format A single set of buses / same bus for instructions & data (to connect CPU to Memory and I/O) (2 marks - 1 for each, max 2) Accept acronyms ALU, CUMark yourself: how many marks did you get?/ 2 - Question 13H446/01 · June 20182 marks
Describe one feature, not part of the standard Von Neumann Architecture, which contemporary CPUs may have in order to improve performance.
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Two separate areas of memory... one for instructions & one for data (Harvard) - 1 mark for feature, 1 for description Pipelining... whilst an instruction is being executed the next can be decoded - 1 mark for feature, 1 for description Use of Cache... A small amount of high performance memory - 1 mark for feature, 1 for description Multiple Cores... Each core acts as a separate processing unit - 1 mark for feature, 1 for description (2 marks - 1 for identifying feature, 1 mark for description) Accept any reasonable description.Mark yourself: how many marks did you get?/ 2 - Question 14H446/01 · June 20186 marks
A digital coffee making machine has a CPU that uses the Little Man Computer Instruction Set. Part of the coffee making machine's code asks the user to press a button to select strength. The code outputs 1, which will switch on a green light to indicate a valid selection, or outputs 0 to indicate an invalid selection. The code is shown in Fig. 1. Explain which registers and buses are used, and the values they store/carry, when the line LDA redLight is executed (after it has been fetched and decoded). You should assume the address redLight refers to memory location 11.
INP STA entry LDA max SUB entry BRP accept LDA redLight BRA printAndEnd accept LDA greenLight printAndEnd OUT HLT greenLight DAT 1 redLight DAT 0 max DAT 5 entry DATFig. 1 Show mark scheme
The value 11 is stored in the MAR 11 is sent down the address bus A read signal is sent down the control bus 0 is sent (back from memory) down the data bus 0 is stored in the MDR ...and then copied to the ACC (6 marks - 1 mark per bullet, max 6)Mark yourself: how many marks did you get?/ 6 - Question 15H446/01 · June 20171 mark
An architect firm specialises in designing skyscrapers. The firm uses high end computers with high performance CPUs, GPUs and large amounts of RAM. State one characteristic a high performance CPU might have.
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Multiple Cores High / Fast Clock Speed Ability to use pipelining Large Cache Accept concurrency / parallel processing for pipelining (1 mark)Mark yourself: how many marks did you get?/ 1 - Question 16H446/01 · June 20171 mark
State one characteristic a high performance CPU might have.
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Multiple Cores High / Fast Clock Speed Ability to use pipelining Large Cache Accept concurrency / parallel processing for pipelining (1 mark)Mark yourself: how many marks did you get?/ 1
- 1FDE Cycle (4-6 marks): Name specific registers (PC, MAR, MDR, CIR) and buses (address, data, control)
- 2Common FDE mistake: Registers STORE data, they don't "fetch" or "pass" data
- 3Pipelining: Allows next instruction fetch while previous executes - increases throughput
- 4Von Neumann vs Harvard: Single vs separate memory for data/instructions
- 5Performance factors: Clock speed (heat), cores (software must support), cache (L1 fastest)
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