The Fetch-Decode-Execute Cycle

Definition

The fundamental process by which the CPU retrieves, interprets, and carries out instructions from memory, one after another.

FETCH Phase

1.
The address in the PC (address of the next instruction) is copied to the MAR
2.
The instruction at that address is fetched from RAM into the MDR
3.
The PC is incremented (PC + 1) to point to the next instruction
4.
The instruction is copied from the MDR to the CIR (ready for decoding)

DECODE Phase

5.
The instruction in the CIR is split into opcode (operation) and operand (data/address)
6.
The Control Unit decodes the opcode to determine what operation to perform

EXECUTE Phase

7.
The instruction is executed - this may involve:
•
The ALU performing a calculation
•
Data being read from or written to memory
•
Data being moved between registers

Worked Example

Worked Example: Executing LDA 15

Let's trace through the FDE cycle for the instruction "LDA 15" (Load the value from memory address 15 into the Accumulator).

Initial State:
• PC = 100 (next instruction is at address 100)
• ACC = 0

FETCH Phase:
1. PC (100) is copied to MAR
2. Address 100 sent along address bus
3. Read signal sent on control bus
4. Instruction "LDA 15" fetched from memory to MDR
5. PC incremented to 101
6. "LDA 15" copied from MDR to CIR

DECODE Phase:
7. CIR splits into: opcode = "LDA", operand = "15"
8. Control Unit decodes: "LDA" = Load value from memory address into ACC

EXECUTE Phase:
9. Operand (15) copied to MAR
10. Address 15 sent along address bus
11. Read signal sent on control bus
12. Value at address 15 fetched to MDR (let's say value is 42)
13. Value (42) copied from MDR to ACC

Final State:
• PC = 101 (ready for next instruction)
• ACC = 42 (loaded from memory)
• MAR = 15
• MDR = 42

Key Point: Notice how the FDE cycle uses registers and buses in a specific sequence. The MAR and MDR are used twice - first to fetch the instruction, then to fetch the data.

Exam Tip

Common Mistake: Students often forget that the PC is incremented during the FETCH phase, not after EXECUTE. The PC always points to the NEXT instruction.

How the Cycle Affects Each Register

Register	What happens to it during the cycle
PC	Its contents are copied to the MAR at the start of the fetch phase and it is then incremented. A branch instruction overwrites it with a new address during the execute phase
MAR	Receives the address from the PC during the fetch phase. During the execute phase it receives the address held in the operand if data has to be read from or written to memory
MDR	Receives the instruction read from memory during the fetch phase. During the execute phase it holds the data that has just been read from memory or is about to be written to it
CIR	Receives the instruction from the MDR and holds it while it is split into opcode and operand and decoded
ACC	Receives the result of a calculation from the ALU, or data loaded from memory through the MDR. A conditional branch checks its value, and input and output pass through it

Exam Tip

A branch instruction changes the PC during the execute phase. A conditional branch such as BRZ checks the value in the accumulator first, and only changes the PC if the condition is met.

Registers hold values. Write that the address is copied to the MAR and sent along the address bus, not that the MAR fetches the instruction.

FETCH Phase

DECODE Phase

EXECUTE Phase

How the Cycle Affects Each Register

Exam questions on The Fetch-Decode-Execute Cycle

Past paper questions