| Cycle | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 |
|---|---|---|---|---|---|---|---|---|---|
| Inst 1 | F | D | E | ||||||
| Inst 2 | F | D | E | ||||||
| Inst 3 | F | D | E |
| Cycle | 1 | 2 | 3 | 4 | 5 |
|---|---|---|---|---|---|
| Inst 1 | F | D | E | ||
| Inst 2 | F | D | E | ||
| Inst 3 | F | D | E |
3 instructions complete in 5 cycles instead of 9!
| Advantage | Disadvantage |
|---|---|
| Increases instruction throughput | Pipeline stalls if one stage takes longer |
| Better utilisation of CPU components | Branch instructions cause pipeline flushes |
| No increase in clock speed needed | Adds complexity to CPU design |