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Pipelining

1.1.1 Structure and function of the processor · Paper 1 · 1 flashcard · 2 questions

Definition
A technique that improves CPU efficiency by overlapping the execution of multiple instructions. While one instruction is being executed, the next is being decoded, and another is being fetched.
Without Pipelining:
Cycle123456789
Inst 1FDE
Inst 2FDE
Inst 3FDE
With Pipelining:
Cycle12345
Inst 1FDE
Inst 2FDE
Inst 3FDE

3 instructions complete in 5 cycles instead of 9!

AdvantageDisadvantage
Increases instruction throughputPipeline stalls if one stage takes longer
Better utilisation of CPU componentsBranch instructions cause pipeline flushes
No increase in clock speed neededAdds complexity to CPU design